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Workshop

FPGA & Embedded Systems
Engineering Workshop

HDL-based digital architecture, timing closure, hardware acceleration, and real-time embedded control integration — for engineers building intelligent hardware platforms.

✎ Register Interest
📄 VHDL / Verilog
🔌 FPGA Implementation
⚙ Embedded Firmware
📈 DSP & Acceleration
🎓 Certificate Awarded
pid_controller.vhd — Synthesis Ready
1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3 
4entity pid_ctrl is
5  port(
6    clk  : in std_logic;
7    ref  : in signed(15 downto 0);
8    out_pwm : out std_logic
9  );
10end entity;
11architecture rtl of pid_ctrl
12  -- Kp=64 Ki=8 Kd=2
CLK / PWM Output — Simulation
100MHzClock
LUT 42%Utilisation
0 nsTiming Slack
PassSynthesis
About This Workshop

Workshop Overview

This program provides deep exposure to FPGA-based digital design and embedded system development. Participants learn HDL coding, timing analysis, real-time processing, and hardware-software integration for intelligent electronic systems.

All sessions are built around real-world FPGA applications in power electronics, motor control, and industrial automation — with live simulation, synthesis, and hardware implementation exercises using industry-standard tools.

📄

HDL from First Principles

VHDL & Verilog — from basic syntax to complex digital architectures

🔌

Live FPGA Implementation

Synthesis, timing closure, and hardware verification on real boards

⚙

Embedded Co-Design

FPGA-MCU integration, firmware, and communication protocol implementation

🎓

Completion Certificate

Infigrace Technologies technical certificate awarded on completion

Design Flow

Digital System Architecture

📄

HDL Design

Verilog / VHDL

📈

Simulation

Testbench & verify

⚙

Synthesis

Map & optimise

⏱

Timing Analysis

Closure & constraints

🔌

Implementation

Hardware deploy

Curriculum

Key Learning Modules

Four advanced modules covering the complete FPGA and embedded system design lifecycle — from HDL to hardware-accelerated real-time systems.

01
📄

HDL Programming

  • VHDL & Verilog fundamentals — syntax and design paradigms
  • Combinational and sequential logic design
  • Finite State Machine (FSM) architecture and implementation
  • Testbench development and waveform-based simulation
  • RTL coding best practices and synthesis-ready HDL
02
🔌

FPGA Implementation

  • Synthesis, technology mapping, and LUT optimisation
  • Timing constraints — setup, hold, and clock domain crossing
  • Place and route, timing closure methodology
  • Resource utilisation optimisation — LUT, FF, BRAM, DSP
  • Xilinx Vivado / Intel Quartus hands-on implementation
03
⚙

Embedded Firmware & Integration

  • Microcontroller integration with FPGA via AXI / SPI / UART
  • STM32 / ARM Cortex bare-metal and RTOS firmware
  • Real-time interrupt handling and task scheduling
  • Bootloaders, secure firmware update mechanisms
  • CAN / Modbus / I2C communication protocol stacks
04
📈

Hardware Acceleration & DSP

  • Digital signal processing on FPGA — filters, FFT, decimation
  • Parallel processing architecture for high-throughput systems
  • Real-time data handling — ADC/DAC interfacing and pipeline
  • AI edge deployment concepts — hardware inference basics
  • Digital PID and motor control on FPGA for power electronics
Use Cases

Real-World Applications

🚗

EV Control Systems

Motor control, BMS interface, OCPP communication firmware

🏭

Industrial Automation

PLC-equivalent FPGA controllers, fieldbus and HMI interfaces

⚡

Power Electronics Control

Digital PWM, PID loops, ADC sampling for converter control

📡

IoT Edge Devices

Smart sensors, edge analytics, and cloud-connected intelligent nodes

Workshop Structure

Format & Delivery

⏱

Duration

4–5 Day Advanced Program

📚

Level

Intermediate to Advanced

🌐

Mode

Corporate / University / Online

🎓

Certification

Infigrace Technical Certificate

Program Flow

Three-Phase Structure

📄 HDL & Theory

VHDL / Verilog fundamentals, digital logic design, FSM architecture, and testbench methodology with simulation walkthroughs.

🔌 Synthesis & Hardware Labs

Live Vivado / Quartus sessions — synthesis, timing analysis, resource optimisation, and FPGA deployment on evaluation boards.

⚙ Embedded & System Integration

MCU-FPGA co-design, firmware integration, real-time control loop implementation, and final project demonstration.

Audience

Who Should Attend?

🏭

Industry Professionals

  • FPGA & Digital Design Engineers
  • Embedded Firmware Developers
  • Power Electronics & Control Engineers
  • R&D & Product Design Teams
  • Technical Managers
🏫

Academic Community

  • Graduate Engineering Students
  • Postgraduate (M.Tech / MS) Students
  • Research Scholars (VLSI / Embedded)
  • Faculty & Lab Coordinators
  • Student Technical Clubs
🚀

Emerging Engineers

  • Final Year Engineering Students
  • Startup Technical Founders
  • EV & Automation Technology Learners
  • Embedded Systems Enthusiasts
  • Innovation Community Members
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